Aspects of the present invention relate generally to the field of integrated circuit design, and more specifically to systems and methods to optimize a design layout having dummy or supporting shapes.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit.
As part of the circuit design, collections of shapes forming features or devices are inserted into the circuit design as a programmed cell to perform a predefined function. The connections between the features or devices on the circuit are defined with a netlist.
After or during the design and creation of an IC layout, validation and/or optimization operations are often performed on the IC layout using a set of testing, analysis and validation tools. These operations are conventionally performed in part to detect variations in the as-designed layout that may occur during printing due to the optical and/or chemical nature of the processing used to manufacture the IC. For example, optical distortions during the lithography process may cause variations in feature dimensions (e.g. line widths) that are patterned using masks. Optical proximity correction (OPC) tools make small changes to the layout, for example adjusting line widths or adding rounded corners to the design layout, so that the design layout and the printed circuit more closely align. As part of the validation/optimization process, connectivity errors are identified and corrected.
During layout optimization, where the connected features are placed in the design such that the connection includes shapes that are overlapping, the shapes may be adjusted such that the overlapping shapes share an associated pin. However, for shapes not connected via a net connection, the abutment optimization process is not triggered. As a result, shapes in close proximity are not properly optimized by the conventional abutment procedure and the management of such supporting shapes requires manual manipulation of the design layout. Such manual manipulation is time consuming and often fraught with errors.
Accordingly, there is a need in the art to ensure effective IC design by automatically adding, removing, or otherwise adjusting dummy or supporting shapes and triggering an abutment procedure for those shapes.